As for a power metal insulator semiconductor field effect transistor (MISFET) which is one of power semiconductor devices, power MISFET (hereinafter called Si power MISFET) using a silicon (Si) substrate has been heretofore mainstream.
However, power MISFET (hereinafter called SiC power MISFET) using a silicon carbide (SiC) substrate (hereinafter called an SiC substrate) has higher withstand voltage, compared with the Si power MISFET and the SiC power MISFET can reduce loss more. Therefore, in a field of power saving or environmental consideration type inverter technique, the SiC power MISFET especially attracts notice.
The SiC power MISFET can lower on-resistance at the same withstand voltage, compared with the Si power MISFET. This reason is that silicon carbide (SiC) has breakdown strength equivalent to 7 times of the breakdown strength of silicon (Si) and an epitaxial layer to be a drift layer can be thinned. However, in terms of properties to be acquired from silicon carbide (SiC), it cannot be said yet that sufficient properties are acquired and from a viewpoint of utilizing energy sufficiently efficiently, further reduction of on-resistance is desired.
One of problems to be settled as to on-resistance of SiC power MISFET having double diffused metal oxide semiconductor (DMOS) structure is channel parasitic resistance. In DMOS having low 60-V withstand voltage, channel parasitic resistance is a principal cause of parasitic resistance and in DMOS having high 3300-V withstand voltage, the channel parasitic resistance is also in the second highest place next to drift resistance. Accordingly, as for the SiC power MISFET, the reduction of the channel parasitic resistance is required.
A reason why the channel parasitic resistance is high is that mobility in a channel of an Si plane (0001) to be a channel face of DMOS is low. To settle this problem, in Patent Literature 1, a method of forming a trench by making a groove in a part of a p-type body layer and outside the body layer of DMOS and widening effective channel width is disclosed. Further, to reduce channel parasitic resistance, the utilization of a plane (11-20) and a plane (1-100) where high channel mobility is acquired is considered. To utilize a plane having high channel mobility such as the plane (11-20) and the plane (1-100), MOS having trench type structure is required to be formed on a substrate of the plane (0001). However, as in the trench type DMOS, a gate insulating film and a part of a gate are formed not only in a lower part of the p-type body layer supporting withstand voltage but immediately on a drift layer, an electric field exceeding withstand voltage is applied to the gate insulating film and breakdown is caused. Then, trial to subdue an electric field applied to a gate insulating film is made, having trench structure. Patent Literature 2 discloses a method of subduing an electric field applied to a gate insulating film by forming a part of a p-type body layer in a lower position than the gate insulating film formed in a lower part of a trench.